ABSTRACT :

This paper proposes a new multilevel inverter(MLI) topology that utilizes trinary sequence for the dcsources. It gives maximum output voltage level with minimum dc source and switch count when compared to othersequences, such as symmetric, natural, binary, and quasilinear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dclevels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four activedevices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. THD, efficiency and power losses are determined from the simulation results. The switches are further reduced by combining the level generation and polarity generation parts with modified switching pattern. The proposed systemis simulated in MATLAB/Simulink software.

INTRODUCTION :

Multi levelinverters (MLIs) are gaining recognitionas a superior solution for power electronics in renewable energy integration, flexible ac transmission system (FACTS),motor drives, electric vehicles, and other high power dc–ac conversion applications.The idea of MLI is to approximate sinusoidal waveformsby synthesizing stepped level output voltage waveforms.Advantages of MLI output voltage include the high powerquality with reduced total harmonic distortion (THD), better electromagnetic compatibility, and lower switching lossescompared to conventional two-level output inverter. Neutral point clamped (NPC), flying capacitor (FC), and CascadedH-bridge (CHB) are the most well-known conventional MLIs.NPC and FC MLI have challenges regarding the need of clamping diodes, clamping capacitors, cost of a capacitor bank, voltageimbalance, etc., especially for generating higher voltage levels.Among these three topologies, CHBMLI stands out for its modular structure which makes it easy to be designed, synthesized, and repaired. Despite the popularity of the established MLItopologies, there is an obvious need to reduce the number of required components to generate the desired output voltage leveland waveform quality.MLI can be classified as symmetric and asymmetric depending on the value of dc source. MLIs with hybrid configuration areanother alternative to increase the voltage levels. For example,hybrid MLI topology composed of FC and CHB has been considered. However, the utilization of FC has obvious shortcomings as it requires large electrolytic capacitors and complicatedcontrol strategy to get rid of the capacitor voltage balancingproblem. MLI with asymmetric dc sources are attractinggreat interest of researchers’ community. The main benefit ofthis topology is the ability to achieve high output level usingfewer active and passive components. A standout among themis the reverse voltage circuit, presented. The basicunit comprises two parts—first is the combination of dc sourcesthat are switched to form the positive output voltage level. Thisis called the level generation part. The second part isthe polarity changing circuit that can produce positive and negative output voltage levels. Normally, a full bridge inverter isutilized for this purpose. Based on this concept, many topologies have evolved in both symmetric and asymmetricconditions. Symmetric topology has dc sources ofsame magnitude, while the asymmetric utilizes dc sources ofdifferent voltage magnitudes. A switched-ladder MLIhas been developed for generating the maximum level with thehelp of lesser component. A square T-type has developedby combing the two back to back T-type inverters and few extra switches. Reduced switch topologies have beendeveloped but which can utilizes higher dc sources for generating the required output voltage level. Asymmetric topologiesrequire lesser number of components and are capable of producing higher output voltage levels but with some significantshortcomings. For example, the circuits developed lack the ability to generate all the possible additive and subtractive combination of input dc voltage in the output voltagewaveform. The level generation unit cannot synthesize the voltage level with the difference combination of sources(Vdc2−Vdc1 ). On the other hand, they do not have a currentpath to generate the additive combination (Vdc1+Vdc3 ).

PROBLEM STATEMENT :

In this paper, a new 9-level MLI topology thatcan accommodate the trinary dc source sequence is proposedwith the ability to produce all additive and subtractive combinations of input dc sources in the output voltage waveform.Moreover, it eliminates redundancy switching states, reducingthe control complexity for switching pulses generation. Also, theproposed topology operates at unipolar pulsewidth modulation(PWM), which when compared to bipolar switching, reducesthe carrier count by half.by utilizing the trinary sequence, a9-level MLI can be achieved with only nine switches. Moreover,only four active devices are conducting per voltage level. The switches can be further reduced by combining the level generation and polarity generation parts and thereby reduces the size and cost of the inverter.